Given that today’s advanced chips can contain billions of transistors, 60 miles of copper wiring and 10 billion vertical connections between metal layers, the challenges and potential pitfalls this level of complexity presents are mind-boggling. One major problem on the horizon at 20nm and below is the threat of voids forming in the vertical interconnects commonly called vias.
We are pleased to expand our collaboration with imec to help advance the development of GaN-on-Si (gallium nitride-on-silicon) process and equipment technologies for manufacturing solid state lighting (e.g. LED) and next-generation power electronics components on 8-inch Silicon wafers.