This TEM image taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in cross section. These tiny structures – about 1/5000th of the diameter of an average human hair – are similar to the interconnects used to wire the billions of transistors in next-generation microchips. You can see that each trench is partially filled with copper, all the way to the bottom, with no gaps or voids. This was achieved using Applied’s revolutionary copper reflow technology. For a primer on how interconnects are made and how copper reflow works, see this video.
Given that today’s advanced chips can contain billions of transistors, 60 miles of copper wiring and 10 billion vertical connections between metal layers, the challenges and potential pitfalls this level of complexity presents are mind-boggling. One major problem on the horizon at 20nm and below is the threat of voids forming in the vertical interconnects commonly called vias.
Applied Materials’ Bob Linke, process integration manager, Semitool Business Unit, discusses the Applied Raider GT electrochemical deposition (ECD) system – a significant innovation for fabricating copper interconnects at the 22nm technology node and beyond.