Applied’s newest Integrated Materials Solution solves the challenge of selective tungsten deposition, enabling simultaneous improvements in chip power, performance and area/cost (PPAC) in the most advanced foundry-logic nodes.
With EUV-enabled advances in 2D scaling pushing the limits of conventional materials engineering techniques, a breakthrough is needed to overcome increases in contact resistance and enable continued improvements in chip performance, power and area/cost (PPAC).
My previous blog explained the computing architecture requirements for AI workloads. Now, I take a deep dive into the types of materials engineering breakthroughs needed to enable these new architectures.
Part 2 of my blog series looks at how new materials, materials engineering and 3D design techniques are extending the semiconductor technology roadmap even as classic 2D scaling reaches physical and economic limits.